This invention relates to a nonvolatile semiconductor memory device such as a NOR type flash EEPROM having an automatic programming function and automatic erasing function.
A flash EEPROM capable of electrically reprogramming data has three modes of programming, erasing and reading as basic modes. The program mode is an operation for raising the threshold voltage of a memory cell to a preset value (for example, 5.5 V) or more, and the erase mode is an operation for lowering the threshold voltage of a memory cell to a preset value (for example, in a range of 0.5 to 3.0 V).
Further, in the nonvolatile semiconductor memory device having the automatic programming function and automatic erasing function, whether or not the threshold voltage of the memory cell becomes equal to or higher than 5.5 V is verified, for example, and the data reprogramming operation is automatically effected until the threshold voltage of the memory cell becomes equal to or higher than 5.5 V in the program mode, and whether or not the threshold voltage of the memory cell is set in a range of 0.5 to 3.0 V is verified, for example, and a preset operation is automatically effected until the threshold voltage of the memory cell is set into a range of 0.5 to 3.0 V in the erase mode.
FIG. 1 shows a main portion of a conventional nonvolatile semiconductor memory device having the automatic programming function and automatic erasing function.
A memory cell array 11 includes a plurality of blocks each of which includes NOR type memory cells.
External addresses A0, A1 to A17 are input to a multiplexer 13 directly or via an address register 12. An address counter 16 generates an internal address. The multiplexer 13 supplies one of the external address and internal address to a row decoder 14 and column decoder 15.
Input data is supplied to a data input register 18 and command register 19 via an input/output buffer 17. Data in the data input register 18 is supplied to a memory cell via a column selection circuit 20.
The command register 19 recognizes a command constructed by an address and data and outputs control signals to the address register 12, multiplexer 13, data input register 18 and control circuit 21 according to the command.
The control circuit 21 recognizes the operation mode to be next effected based on the control signal output from the command register 19.
A voltage generating circuit 22 generates various voltages corresponding to the operation modes. A voltage generated from the voltage generating circuit 22 is supplied to the bit lines and the control gates of the memory cells in each operation mode.
A verify circuit 23 verifies whether or not the operation of programming data into or erasing data in a selected memory cell is sufficiently effected and outputs the verification result VERLOK to the control circuit 21.
A final address detecting circuit 24 outputs a detection signal AEND indicating that the final address of each block of the memory cell array 11 is detected or not and a detection signal BEND indicating that the final block of the memory cell array 11 is detected or not.
A timer 25 counts the number of operations of data programming or erasing effected with respect to a selected memory cell. The timer 25 outputs a time-out signal TIME OUT to the control circuit 21 when the number of operations of data programming or erasing effected with respect to a selected memory cell has reached a preset number.
A clock generating circuit 26 generates a clock for controlling the internal operation of the flash EEPROM according to signals such as a write enable signal /WE, chip enable signal /CE, and output enable signal /OE.
Next, various operations such as the automatic programming operation and automatic erasing operation in the flash EEPROM are explained with reference to the following Table 1.
TABLE 1 __________________________________________________________________________ MODE CYCLE 1st 2nd 3rd 4th 5th 6th nth __________________________________________________________________________ PROGRAM ADDRESS 5555 2AAA 5555 P.A. DATA AA 55 A0 P.D. BLOCK ADDRESS 5555 2AAA 5555 5555 2AAA B.A. . . . B.A. ERASING DATA AA 55 80 AA 55 30 30 CHIP ADDRESS 5555 2AAA 5555 5555 2AAA 5555 ERASING DATA AA 55 80 AA 55 10 __________________________________________________________________________ P.A.: Program Address P.D.: Program Data B.A.: BLOCK Erasing Address
(1) First, the Automatic Programming Operation is Explained.
A command for the automatic program mode is constructed by addresses and data fetched into the chip in four successive cycles as shown in Table 1 and FIG. 2.
That is, the command register 19 recognizes the program command in the first to third cycles in an initial period and outputs a control signal to the address register 12 and data input register 18 in the fourth cycle so as to permit the program address P.A. and program data P.D. to be respectively latched in the address register 12 and data input register 18.
Further, when the command register 19 recognizes the program command, it outputs a control signal indicating that the program command is recognized to the control circuit 21 and outputs a control signal to the multiplexer 13 so as to permit the address in the address register 12 to be supplied to the row decoder 14 and column decoder 15.
When receiving the control data, the control circuit 21 controls the operations of the respective circuits to execute the automatic program sequence as shown in FIG. 3.
First, the address counter 16, timer 25 and the like are reset and the internal power supply of the program verify P.V. is set up in the voltage generating circuit 22 (steps ST1 to ST3).
After this, data of a memory cell or memory cells (n memory cells (n is a positive natural number) when the flash EEPROM is of xn type) selected by the program address P.A. is read out (step ST4).
Data of a memory cell (which is hereinafter referred to as a selected memory cell) selected by the program address P.A. is compared with the program data P.D. (step ST5).
That is, the lower limit voltage (for example, 5.5 V) of the threshold voltage which is determined as the programmed state is set as a boundary value, data of the selected memory cell is determined as "0" if the threshold value of the selected memory cell is higher than the boundary value, and data of the selected memory cell is determined as "1" if the threshold value of the selected memory cell is lower than the boundary value.
Then, data of the selected memory cell is compared with the program data P.D. that is, data "0", and if the compared data items coincide with each other, it is determined that the sufficient or effective programmed state is attained, a read set-up process for discharging a boosted voltage generated from a charge pump circuit is effected and then the automatic programming operation is terminated (step ST6).
If data of the selected memory cell does not coincide with the program data P.D., it is determined that the programmed state is insufficient or ineffective and the data programming operation is effected for the selected memory cell (electrons are injected into the floating gate).
The data programming operation is repeatedly effected until data of the selected memory cell becomes equal to the program data P.D. if a preset number Limit is not reached (steps ST7 to ST9).
When the number Cycle of program operations for the selected memory cell has reached the preset number Limit, the automatic programming operation is terminated (steps ST6, ST7) after the read set-up process is effected even if data of the selected memory cell does not coincide with the program data P.D.
In this case, a signal ERROR indicating occurrence of a defective programmed state is set to "1" (step ST10).
(2) Next, the Automatic Erasing Operation is Explained.
The command register 19 recognizes the erase command in the first to fifth cycles in an initial period and recognizes a block of the memory cell array 11 which is subjected to the erase operation based on commands in the sixth and succeeding cycles.
That is, if no command is input in a preset period of time after a command indicating an address of a block to be subjected to the erase operation is input in the sixth or succeeding cycle and a command indicating an address of a pres et block to be subjected to the erase operation is input in the nth cycle, the control circuit 21 controls the operations of the circuits to execute the automatic erase sequence shown in FIG. 4.
Further, the command register 19 outputs a control signal to the multiplexer 13 so as to permit the internal address of the address counter 16 to be supplied to the row decoder 14 and column decoder 15.
As shown in FIG. 4, the automatic erasing operation is constructed by the following three stages.
1. Pre Program PA1 2. Erase PA1 3. Convergence
The pre-program operation is an operation for making equal the threshold values of all of the memory cells in each selected block before erasing. The erase operation is an operation for simultaneously erasing data items of all of the memory cells for each selected block. The convergence operation is an operation for detecting a memory cell or cells in the excessively erased state in each selected block and restoring the threshold value of the memory cell in the excessively erased state to a normal value for each bit line.
The above operations are explained in detail below with reference to FIG. 4.
In the following explanation, a case wherein selection or non-selection is sequentially recognized for each block in all of the blocks of the memory cell array is taken as an example.
First, the address counter 16, timer 25 and the like are reset and the address block BLOCK is set to an initial value "0" (steps ST1, ST2).
Next, whether or not a block selected by the block address BLOCK is a selected block to be subjected to the automatic erasing operation is verified (step ST3).
When the block selected by the block address BLOCK is a non-selected block (which is not subjected to the automatic erasing operation), whether or not a block selected by a next block address BLOCK is a selected block is verified (step ST11).
When the block selected by the block address BLOCK is a selected block, the pre-program operation is effected (step ST4).
The pre-program operation is effected according to the procedure shown by the subroutine of FIG. 5.
First, an address Add of the address counter 16 is set to an initial value "0" and a numeric value (corresponding to the number of program operations) Cycle of the timer 25 is set to an initial value "0" (steps ST41, ST42). Further, in the voltage generating circuit 22, the internal power supply of the program verify P.V. is set up (step ST43).
After this, data of a memory cell or memory cells (n memory cells (n is a positive natural number) when the flash EEPROM is of xn type) selected by the address Add is read out (step ST44).
Data of a memory cell (which is hereinafter referred to as a selected memory cell) selected by the address Add is compared with the program data "0" (step ST45).
That is, the lower limit voltage (for example, 5.5 V) of the threshold voltage which can be verified as the programmed state is set as a boundary value, data of the selected memory cell is determined as "0" if the threshold value of the selected memory cell is higher than the boundary value, and data of the selected memory cell is determined as "1" if the threshold value of the selected memory cell is lower than the boundary value.
Then, if data of the selected memory cell does not coincide with the program data "0", it is determined that the programmed state is insufficient and the data programming operation is effected for the selected memory cell (electrons are injected into the floating gate).
The data programming operation is repeatedly effected until data of the selected memory cell becomes equal to the program data "0" if a preset number Limit is not reached (steps ST48, ST49).
When the number Cycle of programming operations for the selected memory cell has reached the preset number Limit, the pre-program operation is terminated (step ST46) even if data of the selected memory cell does not coincide with the program data.
In this case, a signal ERROR indicating occurrence of a defective programmed state is set to "1" (step ST47).
If data of the selected memory cell coincides with the program data "0", it is determined that the programmed state is sufficient and the address Add is incremented by one, and the same operation is effected for a memory cell selected by a next address. At this time, the value of the timer 25 is reset to the initial value (steps ST42, ST51).
Further, when data of the selected memory cell coincides with the program data "0" and if the address Add is the final address in the block, the pre-program operation is terminated. At this time, the distribution of the threshold values of the memory cells in the selected block is obtained as shown in FIG. 6 (step ST50).
Next, whether the signal ERROR indicating the presence or absence of the defective programmed state is "1" or not is determined, and if the defective programmed state has occurred, that is, if the signal ERROR is "1", a read set-up process for discharging a boosted voltage generated from the charge pump circuit is effected and then the automatic erasing operation is terminated (steps ST5, ST12).
If the pre-program operation is correctly effected, that is, if the signal ERROR is "0", the erase operation is effected (step ST6).
The erase operation is effected according to the procedure shown by the subroutine of FIG. 7.
First, the address Add of the address counter 16 is set to the initial value "0" and the value (corresponding to the number of erasing operations) Cycle of the timer 25 is set to the initial value "0" (steps ST61, ST62). Further, the internal power supply of the erase verify E.V. is set up in the voltage generating circuit 22 (step ST63).
After this, data of a memory cell or memory cells (n memory cells (n is a positive natural number) when the flash EEPROM is of xn type) selected by the address Add is read out (step ST64).
Data of a memory cell (which is hereinafter referred to as a selected memory cell) selected by the address Add is compared with the expected value "1" (step ST65).
That is, the upper limit voltage (for example, 3.0 V) of the threshold voltage which can be verified as the erased state is set as a boundary value, data of the selected memory cell is determined as "0" if the threshold value of the selected memory cell is higher than the boundary value, and data of the selected memory cell is determined as "1" if the threshold value of the selected memory cell is lower than the boundary value.
If data of the selected memory cell does not coincide with the expected value "1", it is determined that the erased state is insufficient and the data erasing operation is effected for all of the memory cells in the selected block (electrons in the floating gates are drawn out).
In this case, the data erasing operation (flash erasing) is effected for all of the memory cells in the selected block and the data erasing operation is a peculiar operation of the flash EEPROM. Therefore, the data erasing operation is effected not only for the selected memory cell but also for the memory cells in which data is already erased.
The erasing operation is repeatedly effected (steps ST66, ST68, ST69) until data of the selected memory cell becomes equal to the expected value "1" if a preset number Limit is not reached.
When the number Cycle of erasing operations for the selected memory cell has reached the preset number Limit, the erase operation is terminated (step ST66) even if data of the selected memory cell does not coincide with the expected value "1".
In this case, a signal ERROR indicating occurrence of a defective erased state is set to "1" (step ST67).
On the other hand, if data of the selected memory cell coincides with the expected value "1", it is determined that the erased state of the selected memory cell is sufficient, and then the address Add is incremented by one and the same operation is effected for a memory cell selected by a next address. At this time, the value of the timer 25 is not reset to the initial value. This is because the erase operation is effected for all of the memory cells (step ST71).
Further, when data of the selected memory cell coincides with the expected value "1" and if the address Add is the final address in the block, the erase operation is terminated. At this time, the distribution of the threshold values of the memory cells in the selected block is obtained as shown in FIG. 8 (step ST70).
Next, whether the signal ERROR indicating the presence or absence of the defective erased state is "1" or not is determined, and if the defective erased state has occurred, that is, if the signal ERROR is "1", a read set-up process for discharging a boosted voltage generated from the charge pump circuit is effected and then the automatic erasing operation is terminated (steps ST7, ST12).
If the erase operation is correctly effected, that is, if the signal ERROR is "0", the convergence operation is effected (step ST8).
The convergence operation is effected according to the procedure shown by the subroutine of FIG. 9.
First, the address (which is used for selecting only a column and none of the rows are selected) Add of the address counter 16 is set to an initial value and the value (corresponding to the number of convergence operations) Cycle of the timer 25 is set to the initial value "0" (steps ST81, ST82). Further, the internal power supply for the leak check LCK. is set up in the voltage generating circuit 22 (step ST83).
After this, the column leak checking process (leak checking of a memory cell for each column) is effected (step ST84).
The column leak checking process is to set all of the rows (word lines) into the non-selected state, set one column into the selected state and check the leak current flowing in the selected column so as to verify whether or not a memory cell in the excessively erased state is present.
That is, if the total sum of the leak currents flowing in all of the memory cells on the selected column is smaller than a reference value, data of the selected column is determined as "0", and if the total sum of the leak currents flowing in all of the memory cells on the selected column is larger than the reference value, data of the selected column is determined as "1".
The leak current occurs in a memory cell which is set in the excessively erased state and whose threshold voltage is lower than 0.5 V. That is, the memory cell set in the excessively erased state permits current flow even if it is not selected (the word line is set at 0 V).
Then, data of the selected column is compared with the expected value "0" (step ST85).
If data of the selected column does not coincide with the expected value "0", it is determined that the convergence state is insufficient and the convergence operation (for eliminating the excessively erased state) is simultaneously effected for all of the memory cells on the selected column.
The convergence operation is repeatedly effected until data of the selected memory cell becomes equal to the expected value "0" if a preset number Limit is not reached (steps ST86, ST88, ST89).
When the number Cycle of convergence operations for the selected column has reached the preset number Limit, the convergence operation is terminated (step ST86) even if data of the selected memory cell does not coincide with the expected value "0".
In this case, a signal ERROR indicating that the convergence operation is not completely effected is set to "1" (step ST87).
On the other hand, if data of the selected column coincides with the expected value "0", it is determined that the sufficient convergence state is attained for all of the memory cell on the selected column and the address Add is incremented by one, and the same operation is effected for memory cells on a next column (step ST91).
Further, when data of the selected column coincides with the expected value "0" and if the address Add is an address for selecting the final column in the block, the convergence operation is terminated.
When the convergence operation for all of the columns is terminated, the distribution of the threshold values of the memory cells in the selected block is obtained as shown in FIG. 10 (step ST90).
Next, whether or not the signal ERROR indicating that the convergence operation is not completely effected is set at "1" is determined, and if the signal ERROR is "1", the read set-up process for discharging the boosted voltage generated from the charge pump circuit is effected and then the automatic erasing operation is terminated (steps ST9, ST12).
If the signal ERROR is "0", whether the selected block is a final block or not is determined and if it is determined that the selected block is the final block, the automatic erasing operation is terminated after the read set-up process is effected, and if the selected block is not the final lock, the above-described operation is effected for a next block (steps ST10 to ST12).
The above explanation is made for a case of block erasing, but the above-described automatic erase sequence can be used as it is for a case of chip erasing, and at this time, it is only necessary to set all of the blocks in the selected state in the above-described automatic erase sequence.
(3) Next, the Other Operation is Explained.
In the flash EEPROM, various types of test operations are provided in addition to the above-described automatic programming operation and automatic erasing operation.
FIG. 11 shows the sequence of the program test operation and the subroutine of FIG. 5 is used for the "Pre-Program" operation in the step ST4. FIG. 12 shows the sequence of the erase test operation and the subroutine of FIG. 7 is used for the "Erase" operation in the step ST4. FIG. 13 shows the sequence of the convergence test operation and the subroutine of FIG. 9 is used for the "Convergence" operation in the step ST4.
Conventionally, in the flash EEPROM described above, one of the automatic programming operation, automatic erasing operation and test operations to be next effected is determined by supplying one of inherent commands which respectively correspond to the above operations to the memory chip from the exterior of the memory chip and identifying the command as shown in Table 1.
Further, in order to determine the operation to be next effected based on the command inherent to the corresponding operation, the sequences of the automatic programming operation, automatic erasing operation and test operations are independently set as shown in FIGS. 3, 4, 11 to 13.
Therefore, a circuit for inputting and identifying the command for determining the operation of the flash EEPROM becomes complicated and large in size and the control operation in the control circuit for controlling the operations of various circuit sections becomes complicated.